1. Field of the Invention
The present invention relates to semiconductor storage devices and more particularly to a semiconductor storage device in which a cell array and a word driver are formed on isolate wells.
2. Description of Related Art
A semiconductor storage device (which is referred to hereinafter as a memory) is used as a storage device in various equipment. There is a strong need for a memory used in portable devices to exhibit low power consumption. However, as the manufacturing process of semiconductor elements constituting a memory is shifted to finer design rules, leakage current of semiconductor elements increases to result in higher power consumption. Further, the increase in leakage current requires increasingly frequent refresh operation for DRAM (Dynamic Random Access Memory) to maintain memory, which further increases power consumption.
In order to reduce the leakage current, a back-gate voltage VBB to be applied to a back gate of a gate transistor of a memory cell is set to a lower voltage (i.e. a negative voltage) than a substrate voltage (which is typically a ground voltage). A technique to set a back-gate voltage VBB to be lower than a substrate voltage is disclosed in Japanese Unexamined Patent Publication No. 6-37281 (referred to hereinafter as the related art 1).
FIG. 5 is a circuit diagram of a memory according to the related art 1. As shown in FIG. 5, a memory 100 of the related art 1 includes word drivers to drive memory cells disposed in a word driver area 111 and memory cells to store data disposed in a cell array 110. In the word driver, a PMOS transistor P1 and an NMOS transistor N1 are connected in series between a drive voltage Vboot and a charge retention voltage VKK. Control signals CTRL with opposite logic levels to each other are input to the PMOS transistor P1 and the NMOS transistor N1, respectively. The drain of the PMOS transistor P1 and the drain of the NMOS transistor N1 are connected at a node, to which a word line WL is connected. In response to the control signals CTRL, the word driver supplies the drive voltage Vboot to the word line when writing or reading data and supplies the charge retention voltage VKK to the word line WL when holding data. The drive voltage Vboot is higher than the power supply voltage VDD, and the charge retention voltage VKK equals the ground voltage GND.
The memory cell includes a gate transistor and a capacitor C1. The gate transistor may be an NMOS transistor. The gate of the gate transistor is connected to the word line WL, and the drain is connected to a bit line BL. The source of the gate transistor is connected to a reference voltage VVC (e.g. VDD/2) through the capacitor C1. A back-gate voltage VBB of the gate transistor, which is a voltage of a well where the NMOS transistor is formed, is set to a negative voltage that is lower than the ground voltage GND. The bit line BL is connected to a sense amplifier (not shown) and the charge of the capacitor C1 is output from the sense amplifier through the bit line BL.
Data is written to or read from the memory cell by bringing the gate transistor into conduction according to the voltage of the word line WL. The charges accumulated in the capacitor are maintained by bringing the gate transistor into non-conduction.
FIG. 6 shows a schematic diagram of a block layout of the memory 100. As shown in FIG. 6, the memory 100 of the related art 1 includes a cell array 110 where a plurality of memory cells are placed, a word driver area 111 where a plurality of word drivers are placed, a sense amplifier area 112 where a plurality of sense amplifiers are placed, and a crossing area 113 where a junction circuit to transfer a control signal from a controller (not shown) to the word drivers and the sense amplifiers is placed. The cell array 110, the word driver area 111, the sense amplifier area 112 and the crossing area 113 are isolated by a isolation area 114. The cell array 110, the word driver area 111, the sense amplifier area 112 and the crossing area 113 constitute one array set, and a plurality of array sets are arranged in a lattice pattern in the memory 100 of the related art 1.
FIG. 7 is a cross-sectional view of the memory 100 along line A-A′ in FIG. 6. As shown in FIG. 7, in the memory 100, a deep N-well area 121 formed of an N-type semiconductor is placed in an upper layer of a substrate area P-sub 120 formed of a P-type semiconductor. A P-well area 122 where a cell array is formed is placed in an upper layer of the deep N-well area 121. In the upper layer of the deep N-well area 121 is also placed a part of an N-well area 125 to serve as the isolation area 114 in the vicinity of the P-well area 122 where a cell array is formed. The word driver area 111 is placed between the adjacent isolation areas 114. The word driver area 111 is formed in a well that is formed in the upper layer of the substrate area P-sub 120. For example, a P-well area 123 where an NMOS transistor is placed adjacent to the isolation area 114, and an N-well area 124 where a PMOS transistor is formed is placed between the P-well areas 123.
In the memory of the related art 1, the P-well area 122 where the cell array 110 is formed is isolated from the substrate area P-sub 120 and the word driver area 111 by the N-well areas 121 and 125, so that the back-gate voltage VBB of the gate transistor of the memory cell is a negative voltage.
A technique of reducing the layout area of the memory 100 of the related art 1 by reducing the isolation area 114 is disclosed in Japanese Unexamined Patent Publication No. 11-17134 (referred to hereinafter as the related art 2). FIG. 8 shows a circuit diagram of a memory 200 according to the related art 2. The memory 200 is substantially the same as the memory 100 except that the charge retention voltage VKK of the memory driver 200 connected to the word driver equals the back-gate voltage VBB while the charge retention voltage VKK equals the ground voltage GND in the memory 100.
FIG. 9 shows a schematic diagram of a block layout of the memory 200 according to the related art 2. As shown in FIG. 9, in the memory 200, a cell array 210, a word driver area 211, a sense amplifier area 212 and a crossing area 213 are arranged without a isolation area interposed therebetween. FIG. 10 is a cross-sectional view along line A-A′ in FIG. 9.
As shown in FIG. 10, in the memory 200, a deep N-well area 221 is placed in an upper layer of a substrate area P-sub 220 formed of a P-type semiconductor. The cell array 210 and the word driver area 211 are placed in an upper layer of the deep N-well area 221. In the cell array 210 and the word driver area 211, an N-well area 223 where a PMOS transistor of the word driver area is formed is placed adjacent to a P-well area 222 where one cell array 210 is formed. A P-well area 224 where an NMOS transistor of the word driver area 211 is formed is integrated with a P-well area 222 where another cell array 210 is formed.
In the memory 200, one cell array 210 and the word driver area 211 are insulated from each other with the semiconductors having opposite polarities placed adjacently, and the other cell array 210 and the word driver area 211 are connected without a isolation area with the semiconductors having the same polarity placed adjacently. Such a layout achieves the reduction of a chip area while setting the back-gate voltage VBB of the cell array 210 to a negative voltage.
However, if the gate transistor of the memory cell is designed to be finer, leakage current flows even when the gate voltage of the gate transistor is set to the ground voltage GND to bring the transistor into non-conduction. An increase in the leakage current degrades the charge retention characteristics of the memory cell to require increasingly frequent refresh operation, which leads to higher power consumption.
Further, the inventors of the present invention have found by experiment that the leakage current flowing through the gate transistor has temperature characteristics. FIG. 11 shows a graph indicating the leakage current characteristics. As shown in FIG. 11, while the leakage current is minimized when the gate voltage is 0V under low temperature, the leakage current is minimized when the gate voltage is a negative voltage under high temperature. It is thus necessary to control the gate voltage of the gate transistor, which is the charge retention voltage VKK in the above-described related arts, according to temperature in order to minimize the leakage current.
In the memory 100 of the related art 1, it is impossible to control the charge retention voltage VKK because it is fixed to the ground voltage GND. This is because the substrate area P-sub 120 in the lower layer of the word driver area 111 is common to other circuit blocks and therefore changing the voltage can hinder other circuit blocks from operating normally.
In the memory 200 of the related art 2, it is also impossible to control the charge retention voltage VKK independently of the back-gate voltage VBB. This is because the P-well area 224 of the word driver area 211 is integrated with the P-well area 222 of another other cell array 210 and therefore the independent control of the back-gate voltage VBB and the charge retention voltage VKK causes a current to flow from the charge retention voltage VKK to the P-well areas 224 and 222.